1. Field of the Invention
The present invention relates to a semiconductor memory device and, more specifically, it relates to improvements in the arrangement of the memory cells, in the electrical connection structure and in the structure of the capacitor region.
2. Description of the Prior Art
A semiconductor memory device comprises capacitors in which information is stored, transistors which are switched by corresponding word lines for inputting (writing) and outputting (reading) information to and from the corresponding capacitors, and bit lines connected to the transistors for transmitting the information.
FIG. 4A shows a schematic plan view of a conventional dynamic type semiconductor memory device. FIG. 4B is a cross sectional view taken along a line B--B of FIG. 4A. In these figures, a source region 6a and drain regions 6b of transistors 6 are formed on a main surface of a silicon substrate 1 and capacitor regions 4a are provided adjacent to the drain regions 6b. These regions are surrounded by an isolating region 7 and a channel cut 8 is formed below the isolating region 7. Over channel regions 3a provided between the source region 6a and the drain regions 6b, word lines 3 are formed with corresponding gate insulating films 3b interposed therebetween. A capacitor electrode 9 is formed over the capacitor regions 4a with a capacitor insulating film 4b interposed therebetween. The area on which the capacitor electrode 9 is formed is shown by the hatching of broken lines in FIG. 4A. These word lines 3 and the capacitor electrode 9 are covered with an insulating layer 10. A bit line 5 formed on the insulating layer 10 is connected through a contact hole 2 to the source region 6a which is common to the two transistors 6. Namely, two capacitors 4a are connected to one bit line 5 via one contact hole 2 through respective switching transistors 6.
As can be seen from FIG. 4A, a contact hole 2 formed on a source region 6a of another memory connected to the adjacent bit line 5 exist in the vicinity of the outer periphery of one capacitor region 4a. Therefore, if a trench is formed around the capacitor region 4a so as to employ the side wall of the trench also as a capacitor region, the capacitor region on the side wall of the trench is close to and opposed to the transistor region of the adjacent member cell, affecting the characteristics of the transistors.